The present invention relates generally to semiconductor memory devices, and more particularly to semiconductor memory devices having efficient parallel multi-bit testing.
A semiconductor memory device can typically be arranged into a plurality of banks, which may be independently operated. Each bank may be arranged into a plurality of memory cell plates or arrays, which contain memory cells arranged in rows and columns. Memory cells are selected based on row and column address values.
In an independently operable bank, a row of memory cells is selected by a low order address (row address), which is input into a row decoder. From the selected row of memory cells, a specific cell or cells are selected by a high order address (column address), which is input into a column decoder. Thus, a bit from a memory cell or a group of memory cells can be selected in order to be read out of a semiconductor memory device.
In the read operation, data selected by the address value is output from a memory cell array by way of a data line or input/output (I/O) bus. This data can then be received by a data amplifier (DAMP) and output to a read/write bus (RWBS). The data is then output from the semiconductor memory device by way of an output amplifier or buffer.
As an example, in a semiconductor memory arranged into four banks and having 16 data input/output pins, 16 read/write busses (RWBS) and 64 (16xc3x974) data amplifiers (DAMP) will typically exist.
An example of a block diagram showing a semiconductor memory configured with two banks can be seen in FIG. 3.
The semiconductor memory of FIG. 3 contains two independently operable banks (10 and 20) shown as BANK A and BANK B. Each bank (10 and 20) is connected to a data amplifier DAMP 40 by way of an I/O bus (IOAT/N and IOBT/N). Each bank (10 and 20) includes its own DAMP 40. This allows increased operating speed of the semiconductor memory by reducing the length of the I/O bus from the memory cell array to the DAMP. Read/write bus RWBST/N receives the output of the DAMP 40. Typically, there may be only one read/write bus RWBST/N per data pin on a chip. Thus in the case of 16 external data pins (xc3x9716) there may be only 16 read/write busses RWBST/N. Read/write bus RWBST/N and I/O buses (IOAT/N and IOBT/N) contain both a xe2x80x9ctruexe2x80x9d and a xe2x80x9cnot truexe2x80x9d line, which carry data and complementary data.
In a normal read operation only one DAMP 40 is enabled per read/write bus RWBST/N. This is based on a data amplifier enable signal DAE, which will be activated in accordance with the activated bank (10 or 20). Thus, it can be seen that BANK A 10 and BANK B 20 can share the same read/write bus RWBST/N on which data may be read out of either bank (10 or 20).
However, in order to decrease test time in a production part, parallel test schemes are implemented that allow multiple bits to be read in parallel, compared with each other and the result of the comparison being output on a data pin. This will allow for instance a xc3x9716 device to have 32 bits being tested in one read cycle which will increase the test throughput, thus reducing test time and therefore reducing manufacturing costs.
In the configuration of FIG. 3, a parallel test mode can be implemented by activating both banks (10 and 20) and allowing both DAMPs 40 to be activated and operate as a wired-OR/NOR with read/write bus RWBST/N being the output. This can be accomplished by precharging the complementary data line of read/write bus RWBST/N to a high logic/voltage level and having each DAMP 40 pull down (apply a low logic/voltage level) either the xe2x80x9cTxe2x80x9d or xe2x80x9cNxe2x80x9d depending on whether the data received from the bank (10 and 20) was a zero or one logic value. In the parallel test mode, the same data logic value is output from each bank (10 and 20) indicating a xe2x80x9cpassxe2x80x9d=0 condition in which only one data line from the read/write bus RWBST/N is pulled down. However, if BANK A 10 outputs a different data logic value than BANK B 20, one DAMP 40 will pull down one of the data lines from the read/write bus RWBST/N and the other DAMP 40 will pull down the other data line from the read/write bus, thus indicating a xe2x80x9cfailxe2x80x9d condition. The xe2x80x9cpassxe2x80x9d or xe2x80x9cfailxe2x80x9d condition can then be detected by detection circuitry (not shown).
Referring to FIG. 4, a circuit schematic diagram of the conventional data amplifier DAMP 40 is set forth. The conventional data amplifier DAMP 40 can be used in the semiconductor memory of FIG. 3.
The conventional data amplifier 40 includes differential amplifiers (D1-D3), inverters (L20 and L21), 2-input NOR gates (L22 and L23), and pull down n-channel insulated gate field effect transistors (IGFETs) (N5 and N6). The top conventional data amplifier 40 illustrated in FIG. 4, corresponds to DAMP 40 connected to BANK A 10 in FIG. 3. FIG. 4 also includes the bottom conventional data amplifier 40 drawn as a box with only pull down IGFETs (N7 and N8) illustrated, however, it is understood that the bottom conventional data amplifier 40 includes the same elements as the top conventional data amplifier 40. The bottom conventional data amplifier 40 corresponds to DAMP 40 connected to BANK B 20 in FIG. 3.
The top conventional data amplifier 40 receives data I/O line IOAT and complementary data I/O line IOAN from BANK A 10 as inputs. Top conventional data amplifier 40 also receives data amplifier enable signal DAEA as an input and has outputs connected to read/write bus RWBST/N.
The operation of conventional data amplifier 40 will be explained with reference to the conventional data amplifier connected to BANK A 10. When data amplifier enable signal DAEA is at a low logic level, top conventional data amplifier 40 of FIG. 4 is disabled. The low logic level of data amplifier enable signal DAEA is applied to differential amplifiers (D1-D3) thus placing the differential amplifiers (D1-D3) in a disable state. The low logic level of data amplifier enable signal DAEA propagates through inverter L20 and 2-input NOR gates (L22 and L23) to force the gates of n-channel IGFETs (N5 and N6) to a logic low level, thus placing n-channel IGFETs (N5 and N6) in a non-conducting state.
When data amplifier enable signal DAEA is at a high logic level differential amplifiers (D1 to D3) are enabled. Differential amplifier D1 receives data line IOAT at a positive input terminal and complementary data line IOAN at a negative input terminal while differential amplifier D2 receives data line IOAT at a negative input terminal and complementary data line IOAN at a positive input terminal. The outputs of differential amplifier D1 and differential amplifier D2 are then applied to the positive and negative input terminals of differential amplifier D3 respectively. In this manner, by applying I/O bus IOAT/N to differential amplifiers (D1 and D2) in a complementary fashion, variations in the process or layout of the differential amplifiers (D1 and D2) that may cause an imbalance can be cancelled. The output of differential amplifier D3 is then applied to the gate of n-channel IGFET N5 by way of 2-input NOR gate L22. The output of differential amplifier D3 is also applied to the gate of n-channel IGFET N6 by way of inverter L21 and 2-input NOR gate L22. In this manner, if I/O bus IOAT/N carries logical one data, the gate of n-channel IGFET N5 will remain low and the gate of n-channel IGFET N6 will become high, thus discharging read/write bus line RWBSN. However, if I/O bus IOAT/N carries logical zero data, the gate of n-channel IGFET N6 will remain low and the gate of n-channel IGFET N5 will become high, thus discharging read/write bus line RWBST.
It is understood that the bottom conventional data amplifier 40 operates in the same manner as the top conventional data amplifier 40 except the bottom conventional data amplifier 40 has inputs corresponding to BANK B 20 instead of BANK A 10.
The minimum number of data amplifiers 40 required corresponds to the number of data output pins on the chip. However, as mentioned, in order to improve speed the semiconductor memory of FIG. 3 includes a data amplifier 40 per pin in every bank. This also will allow a parallel test mode in which more than one data bit can be tested per data output pin in one read operation, thus allowing a reduction test time and reducing manufacturing costs.
However, when data amplifiers 40 are arranged in every bank, die or chip size is increased, thus increasing manufacturing costs because fewer chips can be printed on a single wafer.
Thus, there are two conflicting parameters, one is the desire to increase the number of bits that can be tested in one cycle in order to increase test throughput. The other is the desire to have a small chip size. If a single data amplifier is used per data output pin (a data amplifier is shared among different banks), then the chip size is reduced. However, then the number of bits that can be tested in one cycle is limited to a bit per data output pin. Alternatively, if more data amplifiers are placed on the chip, for example, one per bank per data output pin, then a parallel test can improve test throughput, but chip size is increased.
In view of the above discussion, it would be desirable to provide a semiconductor memory in which a data amplifier can process more than one bit of data when in a parallel test mode thereby allowing high test throughput without greatly increasing chip size.
According to the present embodiments, a semiconductor memory device includes a normal read mode and a parallel test mode of operation. The semiconductor memory device includes a plurality of banks coupled to a data amplifier. In the normal mode of operation the data amplifier selects data from one of the banks and outputs it to a read/write bus. In the parallel test mode, the data amplifier compares data from a plurality of the banks and outputs a comparison result.
According to one aspect of the embodiments, the data amplifier includes a selection circuit that selects data from one memory bank in a normal mode of operation and selects data from a plurality of banks in a parallel test mode of operation. The selection circuit can include selection gates that select data according to a selection control signal or a bank address.
According to another aspect of the embodiments, the selection circuit can include a multiplexer that can select data according to a bank address.
According to another aspect of the embodiments, the data amplifier can include a data sense circuit that can amplify one bit of selected data in a normal mode of operation and can amplify a plurality of selected data bits in a parallel test mode of operation.
According to another aspect of the embodiments, the data sense circuit can include a plurality of amplifier circuits such as differential amplifiers that may be configured in a cascaded manner to amplify one bit of selected data in a normal mode of operation and configured to operate individually to amplify a plurality of selected data bits in a parallel test mode of operation.
According to another aspect of the embodiments, the data sense circuit can include a configuration circuit that in response to a test signal can configure a plurality of amplifier circuits to operate individually to amplify a plurality of data bits or in a cascaded manner to amplify a single data bit.
According to another aspect of the embodiments, the data amplifier may include a data output circuit that outputs selected data to a read/write bus in a normal mode of operation. The data amplifier may be disabled in the parallel test mode of operation.
According to another aspect of the embodiments, the data amplifier may include a comparator that compares the plurality of data bits outputted from the data sense circuit in the parallel test mode of operation and generates a comparison result on a read/write bus. The data amplifier may include pull down n-channel transistors operating in a wired NOR configuration with pull down n-channel transistors that may be included in the data output circuit.
According to another aspect of the invention, the comparator may operate to discharge a read/write bus when there is a comparison fail result and may output data when there is a comparison pass result.
According to another aspect of the invention, the comparator may operate to output a logic one when there is a comparison pass result and output a logic zero when there is a comparison fail result.
According to another aspect of the invention, the data amplifier may include a control circuit that receives a parallel test mode signal and a data amplifier enable signal. The control circuit can generate an amplifier enable signal to be received by a data sense circuit. The control circuit can further generate a data output circuit enable signal to be received by a data output circuit. The control circuit can generate a comparator enable signal to be received by a comparator circuit. The control circuit can include a delay element for delaying the generation of the comparator enable signal.